1. Hyperblock Scheduling for Verified High-Level Synthesis;Proceedings of the ACM on Programming Languages;2024-06-20
2. Survival of the Fastest: Enabling More Out-of-Order Execution in Dataflow Circuits;Proceedings of the 2024 ACM/SIGDA International Symposium on Field Programmable Gate Arrays;2024-04
3. Subgraph Extraction-Based Feedback-Guided Iterative Scheduling for HLS;2024 Design, Automation & Test in Europe Conference & Exhibition (DATE);2024-03-25
4. Scheduling and Physical Design;Proceedings of the 2024 International Symposium on Physical Design;2024-03-12
5. TAPA: A Scalable Task-parallel Dataflow Programming Framework for Modern FPGAs with Co-optimization of HLS and Physical Design;ACM Transactions on Reconfigurable Technology and Systems;2023-12-05