1. L. Li , Y. Song , T. Ikenaga and S. Goto , " Hardware Architecture Design of CABAC Codec for H.264/AVC," 2007 International Symposium on VLSI Design , Automation and Test (VLSI-DAT) , 2007 , pp. 1 -- 4 . L. Li, Y. Song, T. Ikenaga and S. Goto, "Hardware Architecture Design of CABAC Codec for H.264/AVC," 2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), 2007, pp. 1--4.
2. Jian-Wen Chen et al , " A hardware accelerator for context-based adaptive binary arithmetic decoding in H.264/AVC," 2005 IEEE International Symposium on Circuits and Systems , 2005 , pp. 4525 -- 4528 Vol. 5 . Jian-Wen Chen et al, "A hardware accelerator for context-based adaptive binary arithmetic decoding in H.264/AVC," 2005 IEEE International Symposium on Circuits and Systems, 2005, pp. 4525--4528 Vol. 5.
3. B. Peng et al , " A hardware CABAC encoder for HEVC," 2013 IEEE International Symposium on Circuits and Systems (ISCAS) , 2013 , pp. 1372 -- 1375 . B.Peng et al, "A hardware CABAC encoder for HEVC," 2013 IEEE International Symposium on Circuits and Systems (ISCAS), 2013, pp. 1372--1375.
4. Hardware implementation of HEVC CABAC encoder
5. Tran , D. , Pham , V. , Nguyen , H.K. , & Tran , X. ( 2019 ). A Survey of High-Efficient CABAC Hardware Implementations in HEVC Standard . Tran, D., Pham, V., Nguyen, H.K., & Tran, X. (2019). A Survey of High-Efficient CABAC Hardware Implementations in HEVC Standard.