Investigating cache energy and latency break-even points in high performance processors

Abstract

In this work we study how cache complexity impacts energy and performance in high performance processors. Moreover, we estimate cache energy budget for two high performance processors. We calculate energy and latency break-even points for realistic and ideal cache organizations for different applications. We show that design efforts made to reduce cache miss rate are only justifiable from the energy and performance point of view only if the associated latency and energy overhead remain below the calculated break-even points. Furthermore, we show that, for the processors and applications studied here, the instruction cache has a lower latency break-even point compared to the data cache. However, investing energy in the data cache is likely to result in better energy efficiency compared to the instruction cache. We also study alternative cache configurations for different processors and investigate if such alternatives would improve energy efficiency.