1. The effect of LUT and cluster size on deep-submicron FPGA performance and density
2. A. Avizienis . 1961. Signed-Digit Number Representations for Fast Parallel Arithmetic. IRE Transactions on Electronic Computers , Vol. EC-10 , 3 ( 1961 ), 389--400. https://doi.org/10.1109/TEC.1961.5219227 10.1109/TEC.1961.5219227 A. Avizienis. 1961. Signed-Digit Number Representations for Fast Parallel Arithmetic. IRE Transactions on Electronic Computers , Vol. EC-10, 3 (1961), 389--400. https://doi.org/10.1109/TEC.1961.5219227
3. F. M. Bianchi S. Scardapane S. Løkse and R. Jenssen. 2020. Reservoir Computing Approaches for Representation and Classification of Multivariate Time Series. IEEE Transactions on Neural Networks and Learning Systems (2020) 1--11. F. M. Bianchi S. Scardapane S. Løkse and R. Jenssen. 2020. Reservoir Computing Approaches for Representation and Classification of Multivariate Time Series. IEEE Transactions on Neural Networks and Learning Systems (2020) 1--11.
4. Yu Cao. [n.d.]. Predictive Technology Model. http://ptm.asu.edu/ (accessed Aug 26 2020). Yu Cao. [n.d.]. Predictive Technology Model. http://ptm.asu.edu/ (accessed Aug 26 2020).
5. ASAP7: A 7-nm finFET predictive process design kit