AutoBench: Automatic Testbench Generation and Evaluation Using LLMs for HDL Design

Author:

Qiu Ruidi1ORCID,Zhang Grace Li2ORCID,Drechsler Rolf3ORCID,Schlichtmann Ulf1ORCID,Li Bing4ORCID

Affiliation:

1. Technical University of Munich

2. TU Darmstadt

3. University of Bremen

4. University of Siegen

Publisher

ACM

Reference25 articles.

1. 2013. IEEE Standard for SystemVerilog-Unified Hardware Design, Specification, and Verification Language. IEEE Std 1800-2012 (Revision of IEEE Std 1800-2009) (2013).

2. Jason Blocklove, Siddharth Garg, Ramesh Karri, and Hammond Pearce. 2023. Chip-Chat: Challenges and Opportunities in Conversational Hardware Design. In ACM/IEEE Workshop on Machine Learning for CAD (MLCAD).

3. Kaiyan Chang, Ying Wang, Haimeng Ren, Mengdi Wang, Shengwen Liang, Yinhe Han, Huawei Li, and Xiaowei Li. 2023. ChipGPT: How Far Are We From Natural Language Hardware Design. arXiv preprint:2305.14019 (2023).

4. Mark Chen, Jerry Tworek, Heewoo Jun, Qiming Yuan, Henrique Ponde de Oliveira Pinto, Jared Kaplan, Harri Edwards, Yuri Burda, Nicholas Joseph, Greg Brockman, et al. 2021. Evaluating Large Language Models Trained on Code. arXiv preprint: 2107.03374 (2021).

5. Machine Learning in Advanced IC Design: A Methodological Survey

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