(Invited) Redefining Outliers for On-Wafer Electrical Testing

Author:

Shintani Michihiro1ORCID,Sato Takashi2ORCID

Affiliation:

1. Kyoto Institute of Technology, Kyoto, Japan

2. Kyoto University, Kyoto, Japan

Funder

JSPS KAKENHI

Publisher

ACM

Reference18 articles.

1. Ali Ahmadi et al. 2014. Spatio-Temporal Wafer-Level Correlation Modeling with Progressive Sampling: A Pathway to HVM Yield Estimation. In Proceedings of IEEE International Test Conference. 18.1.

2. Automotive Electronics Council. 2011. AEC-Q001 Rev-D GUIDELINES FOR PART AVERAGE TESTING. http://www.aecouncil.com/Documents/AEC_Q001_Rev_D.pdf

3. Eli Bingham et al. 2018. Pyro: Deep Universal Probabilistic Programming. Journal of Machine Learning Research (2018), 973--978. Issue 1.

4. W.R. Daasch et al. 2000. Variance Reduction Using Wafer Patterns in IDDQ Data. In Proceedings of IEEE International Test Conference. 189--198.

5. Wim Dobbelaere et al. 2016. Analog Fault Coverage Improvement using Final-Test Dynamic Part Average Testing. In Proceedings of IEEE International Test Conference. 3.1.

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