Evaluate the performance changes of processor simulator benchmarks When context switches are incorporated

Abstract

Building state-of-the-art processors is expensive and time consuming. Once the design is finalized and implemented, simulations are used to evaluate functionality and performance of the system. The Sim-alpha processor simulator is one of the most important tools for performance evaluations. Enhancing processor simulators is one of the major research field and many studies are underway related to this area. Current, open source, processor simulators do not account for the influences caused by multi-processing. In this study, we had shown that most processor simulations only test one program at a time on a virtual processor. The goal of the project was to demonstrate how processor simulators work when external influences are incorporated. Hardware or software interrupts are events that alter sequence of instructions executed by a processor. A context switch occurs when a multitasking operating system suspends the currently running process, and starts executing another. An additional code was added to the Sim-alpha program to allow for context switch. Benchmarks were executed with and without time slice context switch as well as different time slices. The results had shown that when the number of cycles before flushing the cache increases, the miss rate will decrease. For example if we are flushing the cache every 150 cycles, the cache miss rate is 48% compare to 2% without flushing the cache. The effect of flushing the cache is significant on the cache performance of processor simulators. In real life environments, processor must support multiple processes. We demonstrated with a simple change in the code that these simulators can have a more realistic workload. The effect of flushing the cache is significant on the cache performance of processor simulators. Current models do not account for this and may over estimate the performance gains of a particular processor design.