An energy efficient cache design using spin torque transfer (STT) RAM-Reference-Cited by-同舟云学术

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An energy efficient cache design using spin torque transfer (STT) RAM

Published:2010 Issue: Volume: Page:
ISSN:
Container-title:Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design - ISLPED '10
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Author:

Rasquinha Mitchelle,Choudhary Dhruv,Chatterjee Subho,Mukhopadhyay Saibal,Yalamanchili Sudhakar

Publisher

ACM Press

Cited by 54 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. POEM: Performance Optimization and Endurance Management for Non-volatile Caches;ACM Transactions on Design Automation of Electronic Systems;2024-09-04

2. Efficient Deep Learning Using Non-volatile Memory Technology in GPU Architectures;Embedded Machine Learning for Cyber-Physical, IoT, and Edge Computing;2023-10-01

3. HyGain: High-performance, Energy-efficient Hybrid Gain Cell-based Cache Hierarchy;ACM Transactions on Architecture and Code Optimization;2023-03

4. Evolving Skyrmion Racetrack Memory as Energy-Efficient Last-Level Cache Devices;ACM/IEEE International Symposium on Low Power Electronics and Design;2022-08

5. Optimized fast data migration for hybrid DRAM/STT-MRAM main memory;IEICE Electronics Express;2022-01-10

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