An Improved Compensation Time Control Strategy Based on CrM Mode Boost PFC Converter
Author:
Affiliation:
1. School of Communication Engineering, Chengdu University of Information Technology, China
2. Lattice Art Semiconductor Co., Ltd, China
Funder
Integrated Computing and Chip Security Sichuan Collaborative Innovation Center of Chengdu University of Information Technology
Publisher
ACM
Link
https://dl.acm.org/doi/pdf/10.1145/3577065.3577093
Reference10 articles.
1. An AC–DC LED Driver With a Two-Parallel Inverted Buck Topology for Reducing the Light Flicker in Lighting Applications to Low-Risk Levels
2. Electromagnetic Compatibility (EMC) , Part 3-2: Limits-Limits for Harmonic Current Emissions (Equipment Current ≤ 16 A Per Phase) , Standard IEC 61000-3-2 , 2009 . Electromagnetic Compatibility (EMC), Part 3-2: Limits-Limits for Harmonic Current Emissions (Equipment Current ≤ 16 A Per Phase), Standard IEC 61000-3-2, 2009.
3. A topology survey of single-stage power factor corrector with a boost type input-current-shaper
4. A family of PFC voltage regulator configurations with reduced redundant power processing
5. A review of single-phase improved power quality ac~dc converters
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