Symbolic Elaboration: Checking Generator Properties in Dynamic Hardware Description Languages-Reference-Cited by-同舟云学术

Symbolic Elaboration: Checking Generator Properties in Dynamic Hardware Description Languages

Published:2023-09-21 Issue: Volume: Page:
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Container-title:Proceedings of the 21st ACM-IEEE International Conference on Formal Methods and Models for System Design
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Author:

Pan Peitian¹^ORCID,Jiang Shunning¹^ORCID,Ou Yanghui¹^ORCID,Batten Christopher¹^ORCID

Affiliation:

1. Cornell University, Ithaca, New York, USA

Funder

Semiconductor Research Corporation

Xilinx

Intel Corporation

Publisher

ACM

Link

https://dl.acm.org/doi/pdf/10.1145/3610579.3611076

Reference32 articles.

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2. 2017. IEEE Standard for SystemVerilog-Unified Hardware Design Specification and Verification Language. Online Webpage. https://ieeexplore.ieee.org/document/8299595. 2017. IEEE Standard for SystemVerilog-Unified Hardware Design Specification and Verification Language. Online Webpage. https://ieeexplore.ieee.org/document/8299595.

3. Christiaan Baaij , Matthijs Kooijman , Jan Kuper , Arjan Boeijink , and Marco Gerards . 2010 . Căsh: Structural Descriptions of Synchronous Hardware Using Haskell. Euromicro Conf. on Digital System Design (DSD) (Sep 2010). Christiaan Baaij, Matthijs Kooijman, Jan Kuper, Arjan Boeijink, and Marco Gerards. 2010. Căsh: Structural Descriptions of Synchronous Hardware Using Haskell. Euromicro Conf. on Digital System Design (DSD) (Sep 2010).

4. Chisel

5. Roberto Baldoni , Emilio Coppa , Daniele Cono D'elia , Camil Demetrescu, and Irene Finocchi. 2018 . A Survey of Symbolic Execution Techniques. Comput. Surveys ( 2018). Roberto Baldoni, Emilio Coppa, Daniele Cono D'elia, Camil Demetrescu, and Irene Finocchi. 2018. A Survey of Symbolic Execution Techniques. Comput. Surveys (2018).