UMH-Reference-Cited by-同舟云学术

UMH

Published:2016-12-28 Issue:4 Volume:13 Page:1-25
ISSN:1544-3566
Container-title:ACM Transactions on Architecture and Code Optimization
language:en
Short-container-title:ACM Trans. Archit. Code Optim.

Author:

Ziabari Amir Kavyan¹,Sun Yifan¹,Ma Yenai²,Schaa Dana³,Abellán José L.⁴,Ubal Rafael¹,Kim John⁵,Joshi Ajay²,Kaeli David¹

Affiliation:

1. Northeastern University, Boston, MA

2. Boston University, Boston, MA

3. Northeastern University

4. Universidad Católica San Antonio de Murcia, Murcia, Spain

5. KAIST, South Korea

Abstract

In this article, we describe how to ease memory management between a Central Processing Unit (CPU) and one or multiple discrete Graphic Processing Units (GPUs) by architecting a novel hardware-based Unified Memory Hierarchy (UMH). Adopting UMH, a GPU accesses the CPU memory only if it does not find its required data in the directories associated with its high-bandwidth memory, or the NMOESI coherency protocol limits the access to that data. Using UMH with NMOESI improves performance of a CPU-multiGPU system by at least 1.92 × in comparison to alternative software-based approaches. It also allows the CPU to access GPUs modified data by at least 13 × faster.

Funder

NRF

Spanish MINECO

Publisher

Association for Computing Machinery (ACM)

Subject

Hardware and Architecture,Information Systems,Software

Link

https://dl.acm.org/doi/pdf/10.1145/2996190

Reference55 articles.

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