Affiliation:
1. University of Texas at Austin
2. Chinese University of Hong Kong
Abstract
A switch module
M
with
W
terminals on each side is said to be
universal
if every set of nets satisfying the dimensional constraint (i.e., the number of nets on each side of
M
is at most
W
) is simultaneously rout able through
M
. In this article, we present a class of universal switch modules. Each of our switch modules has 6
W
switches and
switch-module flexibility
three (i.e,
F
s
=3). We prove that no switch module with less than 6
W
switches can be universal. We also compare our switch modules with those used in the Xilinx XC4000 family FPGAs and the
antisymmetric
switch modules (with
F
S
=3) suggested by Rose and Brown [1991]. Although these two kinds of switch modules also have
F
S
=3 and 6
W
switches, we show that they are not universal. Based on combinatorial counting techniques, we show that each of our universal switch modules can accommodate up to 25% more routing instances, compared with the XC4000-type switch module of the same size. Experimental results demonstrate that our universal switch modules improve routability at the chip level. Finally, our work also provides a theoretical insight into the important observation by Rose and Brown [1991] (based on extensive experiments) that
F
S
=3 is often sufficient to provide high routability.
Publisher
Association for Computing Machinery (ACM)
Subject
Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Computer Science Applications
Cited by
45 articles.
订阅此论文施引文献
订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. From Topology to Realization in FPGA/VPR Routing;Proceedings of the 2024 ACM/SIGDA International Symposium on Field Programmable Gate Arrays;2024-04
2. PERA: Power-Efficient Routing Architecture for SRAM-Based FPGAs in Dark Silicon Era;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2023-12
3. Exploring FPGA Switch-Blocks without Explicit Pattern Listing;ACM Transactions on Reconfigurable Technology and Systems;2023-05-17
4. A New Model for Parametrically Evaluating the Routability of GRM FPGA;IEICE Electronics Express;2023
5. An Optimized GIB Routing Architecture with Bent Wires for FPGA;ACM Transactions on Reconfigurable Technology and Systems;2022-12-22