1. The uniform memory hierarchy model of computation
2. Bin Bao and Chen Ding . 2013 . Defensive loop tiling for shared cache . In Proceedings of the International Symposium on Code Generation and Optimization. 1--11 . Bin Bao and Chen Ding. 2013. Defensive loop tiling for shared cache. In Proceedings of the International Symposium on Code Generation and Optimization. 1--11.
3. Guy E. Blelloch , Rezaul A. Chowdhury , Phillip B. Gibbons , Vijaya Ramachandran , Shimin Chen , and Michael Kozuch . 2008 . Provably Good Multicore Cache Performance for Divide-and-Conquer Algorithms (SODA '08) . Society for Industrial and Applied Mathematics, USA, 501--510. Guy E. Blelloch, Rezaul A. Chowdhury, Phillip B. Gibbons, Vijaya Ramachandran, Shimin Chen, and Michael Kozuch. 2008. Provably Good Multicore Cache Performance for Divide-and-Conquer Algorithms (SODA '08). Society for Industrial and Applied Mathematics, USA, 501--510.
4. Beyond Amdahl's Law: An Objective Function That Links Multiprocessor Performance Gains to Delay and Energy
5. Ian Cutress. 2019. The Ice Lake Benchmark Preview: Inside Intel's 10nm. https://www.anandtech.com/show/14664/testing-intel-ice-lake-10nm/2 Ian Cutress. 2019. The Ice Lake Benchmark Preview: Inside Intel's 10nm. https://www.anandtech.com/show/14664/testing-intel-ice-lake-10nm/2