Author:
Aitken Robert,Yeric Greg,Cline Brian,Sinha Saurabh,Shifren Lucian,Iqbal Imran,Chandra Vikas
Cited by
11 articles.
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1. Performance-driven Wire Sizing for Analog Integrated Circuits;ACM Transactions on Design Automation of Electronic Systems;2022-12-24
2. NCTUcell: A DDA- and Delay-Aware Cell Library Generator for FinFET Structure With Implicitly Adjustable Grid Map;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2022-12
3. Design and Aging Challenges in FinFET Circuits and Internet of Things (IoT) Applications;Circadian Rhythms for Future Resilient Electronic Systems;2019-06-13
4. A FinFET-Based Framework for VLSI Design at the 7 nm Node;Energy Efficient Computing & Electronics;2019-01-31
5. ASAP7: A finFET-Based Framework for Academic VLSI Design at the 7 nm Node;Low Power Semiconductor Devices and Processes for Emerging Applications in Communications, Computing, and Sensing;2018-08-06