MIP-based detailed placer for mixed-size circuits
Author:
Li Shuai,Koh Cheng-kok
Cited by
4 articles.
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1. Vertical M1 Routing-Aware Detailed Placement for Congestion and Wirelength Reduction in Sub-10nm Nodes;Proceedings of the 54th Annual Design Automation Conference 2017;2017-06-18
2. Detailed placement for modern FPGAs using 2D dynamic programming;Proceedings of the 35th International Conference on Computer-Aided Design;2016-11-07
3. Eh?Placer;ACM Transactions on Design Automation of Electronic Systems;2016-07-26
4. Placement: From Wirelength to Detailed Routability;IPSJ Transactions on System LSI Design Methodology;2016