TRINE

Author:

Taheri Ebadollah1ORCID,Mahdian Mohammad Amin1ORCID,Pasricha Sudeep1ORCID,Nikdast Mahdi1ORCID

Affiliation:

1. Department of Electrical and Computer Engineering, Colorado State University, Fort Collins, CO, USA

Funder

NSF

Publisher

ACM

Reference25 articles.

1. Ananda Samajdar et al. A systematic methodology for characterizing scalability of dnn accelerators using scale-sim . In ISPASS , 2020 . Ananda Samajdar et al. A systematic methodology for characterizing scalability of dnn accelerators using scale-sim. In ISPASS, 2020.

2. Febin P Sunny et al. A survey on silicon photonics for deep learning . ACM JETC , 2021 . Febin P Sunny et al. A survey on silicon photonics for deep learning. ACM JETC, 2021.

3. Yakun Sophia Shao et al. SIMBA: Scaling deep-learning inference with multi-chip-module-based architecture . In MICRO , 2019 . Yakun Sophia Shao et al. SIMBA: Scaling deep-learning inference with multi-chip-module-based architecture. In MICRO, 2019.

4. Ebadollah Taheri et al. DeFT: A deadlock-free and fault-tolerant routing algorithm for 2.5 d chiplet networks . In DATE , 2022 . Ebadollah Taheri et al. DeFT: A deadlock-free and fault-tolerant routing algorithm for 2.5 d chiplet networks. In DATE, 2022.

5. Yuan Li et al. SPACX: Silicon photonics-based scalable chiplet accelerator for dnn inference . In HPCA , 2022 . Yuan Li et al. SPACX: Silicon photonics-based scalable chiplet accelerator for dnn inference. In HPCA, 2022.

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1. Empowering Image Sensors with Integrated Photonic Neural Networks;2024 IEEE Photonics Society Summer Topicals Meeting Series (SUM);2024-07-15

2. SCRIPT: A Multi-Objective Routing Framework for Securing Chiplet Systems against Distributed DoS Attacks;Proceedings of the Great Lakes Symposium on VLSI 2024;2024-06-12

3. Silicon Photonic 2.5D Interposer Networks for Overcoming Communication Bottlenecks in Scale-out Machine Learning Hardware Accelerators;2024 IEEE 42nd VLSI Test Symposium (VTS);2024-04-22

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