Adaptive Row Addressing for Cost-Efficient Parallel Memory Protocols in Large-Capacity Memories-Reference-Cited by-同舟云学术

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Adaptive Row Addressing for Cost-Efficient Parallel Memory Protocols in Large-Capacity Memories

Published:2016-10-03 Issue: Volume: Page:
ISSN:
Container-title:Proceedings of the Second International Symposium on Memory Systems
language:
Short-container-title:

Author:

Knyaginin Dmitry¹,Papaefstathiou Vassilis¹,Stenstrom Per¹

Affiliation:

1. Chalmers University of Technology, Gothenburg, Sweden

Publisher

ACM

Link

https://dl.acm.org/doi/pdf/10.1145/2989081.2989103

Reference37 articles.

1. Memory scheduling championship 2012. www.cs.utah.edu/~rajeev/jwac12. Memory scheduling championship 2012. www.cs.utah.edu/~rajeev/jwac12.

2. DDR4 SDRAM JEDEC standard. www.jedec.org Sept. 2012. DDR4 SDRAM JEDEC standard. www.jedec.org Sept. 2012.

3. Low Power Double Data Rate 3 (LPDDR3) JEDEC standard. www.jedec.org Aug. 2015. Low Power Double Data Rate 3 (LPDDR3) JEDEC standard. www.jedec.org Aug. 2015.

4. Low Power Double Data Rate 4 (LPDDR4) JEDEC standard. www.jedec.org Nov. 2015. Low Power Double Data Rate 4 (LPDDR4) JEDEC standard. www.jedec.org Nov. 2015.

5. Data reorganization in memory using 3D-stacked DRAM

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