Analysis of vector access performance on skewed interleaved memory

Author:

Chen C.-L.1,Liao C.-K.2

Affiliation:

1. Department of Computer Science, and Information Engineering, National Taiwan University, Taipei, Taiwan, R.O.C.

2. Institute of Electrical Engineering, National Taiwan University, Taipei, Taiwan, R.O.C.

Abstract

Memory interleaving and memory skewing are two hardware approaches to reduce memory access conflict for many advanced computer architectures, while pipelined vector computer covers many commercially available supercomputers. The goal of this paper is to study the vector accessing behavior on skewed interleaved memory under pipelined processing environment. We establish a criterion, called average time delay, to indicate the performance of a vector access; and a criterion, called aggregate average time delay to indicate the performance of a given memory system. Under these criteria, we analyze some memory design problems. These problems centralize how to design a memory system which is cost-effective and has less conflicts for vector accesses. We also propose a software approach to reduce memory access conflict, called dimension extension strategy. This strategy performs very well under our analysis.

Publisher

Association for Computing Machinery (ACM)

Reference13 articles.

1. Illiac IV software and application programming;Kuck D. J.;IEEE Trans. Computers,1968

2. P. M. Kogge The Architecture of Pipelined Computers New York McGraw-Hill 1981. P. M. Kogge The Architecture of Pipelined Computers New York McGraw-Hill 1981.

3. Analysis of memory interference in multiprocessors;Bhandarkar P.;IEEE Trans. Computers,1975

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1. Cache-conscious data placement;ACM SIGOPS Operating Systems Review;1998-12

2. Cache-conscious data placement;ACM SIGPLAN Notices;1998-11

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