Architecture Exploration of Standard-Cell and FPGA-Overlay CGRAs Using the Open-Source CGRA-ME Framework
Author:
Affiliation:
1. University of Toronto, Toronto, ON, Canada
2. UNIST, Ulsan, UNK, Rebublic of Korea
Publisher
ACM
Link
https://dl.acm.org/doi/pdf/10.1145/3177540.3177553
Reference6 articles.
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2. The gem5 simulator
3. Davor Capalija and T. S. Abdelrahman. 2013. A high-performance overlay architecture for pipelined execution of data flow graphs Field Programmable Logic and Applications 2013 23rd Int'l Conference on. IEEE Washington DC USA 1--8. ://dl.acm.org/citation.cfm?id=1356802.1356988 Davor Capalija and T. S. Abdelrahman. 2013. A high-performance overlay architecture for pipelined execution of data flow graphs Field Programmable Logic and Applications 2013 23rd Int'l Conference on. IEEE Washington DC USA 1--8. ://dl.acm.org/citation.cfm?id=1356802.1356988
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