Author:
Shelar Rupesh S.,Patyra Marek
Cited by
8 articles.
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1. An algorithm for obstacle‐avoiding clock routing tree construction with multiple TSVs on a 3D IC;IET Computers & Digital Techniques;2018-11-27
2. Low-Power Clock Tree Synthesis for 3D-ICs;ACM Transactions on Design Automation of Electronic Systems;2017-05-31
3. Clock-Tree-Aware Incremental Timing-Driven Placement;ACM Transactions on Design Automation of Electronic Systems;2016-07-26
4. Quantifying the effect of local interconnects on on-chip power distribution;Microelectronics Journal;2015-03
5. Gated low-power clock tree synthesis for 3D-ICs;Proceedings of the 2014 international symposium on Low power electronics and design;2014-08-11