Author:
Maruyama Naoya,Nomura Tatsuo,Sato Kento,Matsuoka Satoshi
Cited by
78 articles.
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1. Optimizing Stencil Computation on Multi-core DSPs;Proceedings of the 53rd International Conference on Parallel Processing;2024-08-12
2. A shared compilation stack for distributed-memory parallelism in stencil DSLs;Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 3;2024-04-27
3. ConvStencil: Transform Stencil Computation to Matrix Multiplication on Tensor Cores;Proceedings of the 29th ACM SIGPLAN Annual Symposium on Principles and Practice of Parallel Programming;2024-02-20
4. Adaptive Auto-Tuning Framework for Global Exploration of Stencil Optimization on GPUs;IEEE Transactions on Parallel and Distributed Systems;2024-01
5. An Introduction to Heterogeneous SoC Design and Verification “A Conceptual-Level”;Synthesis Lectures on Digital Circuits & Systems;2024