NEWROMAP

Author:

Joseph Jan Moritz1,Baloglu Murat Sezgin1,Pan Yue2,Leupers Rainer1,Bamberg Lennart3

Affiliation:

1. RWTH Aachen University, Germany

2. Georgia Institute of Technology

3. GrAI Matter Labs, The Netherlands

Funder

Federal Ministry of Education and Research (BMBF) and the Ministry of Culture and Science of the German State of North Rhine-Westphalia (MKW) under the Excellence Strategy of the Federal Government and the Länder

Federal Ministry of Education and Research (BMBF)

Publisher

ACM

Reference14 articles.

1. A Hansson etal 2007. Avoiding message-dependent deadlock in network-based systems on chip. VLSI design (2007). A Hansson et al. 2007. Avoiding message-dependent deadlock in network-based systems on chip. VLSI design (2007).

2. C Marcon etal 2005. Exploring NoC mapping strategies: an energy and timing aware technique. In DATE. IEEE. C Marcon et al. 2005. Exploring NoC mapping strategies: an energy and timing aware technique. In DATE. IEEE.

3. 2019;Graves CE;IEEE TNANO,2019

4. 2015. Truenorth: Design and tool flow of a 65 mw 1 million neuron programmable neurosynaptic chip;Akopyan F;IEEE TCAD,2015

5. MAERI

Cited by 4 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Neuron grouping and mapping methods for 2D-mesh NoC-based DNN accelerators;Journal of Parallel and Distributed Computing;2024-11

2. Visual Exploratory Analysis for Designing Large-Scale Network-on-Chip Architectures: A Domain Expert-Led Design Study;IEEE Transactions on Visualization and Computer Graphics;2023

3. EmuNoC: Hybrid Emulation for Fast and Flexible Network-on-Chip Prototyping on FPGAs;2022 32nd International Conference on Field-Programmable Logic and Applications (FPL);2022-08

4. X-Fault: Impact of Faults on Binary Neural Networks in Memristor-Crossbar Arrays with Logic-in-Memory Computation;2022 IEEE 4th International Conference on Artificial Intelligence Circuits and Systems (AICAS);2022-06-13

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