Dual-Level DVFS-Enabled Millimeter-Wave Wireless NoC Architectures

Abstract

Wireless Network-on-Chip (WiNoC) has emerged as an enabling technology to design low power and high bandwidth massive multicore chips. WiNoCs based on small-world network architecture and designed with incorporating millimeter (mm)-wave on-chip wireless links offer significantly lower power and higher bandwidth compared to traditional mesh-based counterparts. In this mm-wave small-world WiNoC (mSWNoC), long distance communication predominately takes place through the wireless shortcuts whereas the short-range data exchange still occurs through the conventional metal wires. This results in performance advantages mainly stemming from using the wireless links as long-range shortcuts between far apart cores. This performance gain can be enhanced further if the wireline links and the processing cores of the WiNoC are optimized according to the traffic patterns and application workloads. In this work, we demonstrate that by incorporating both processor- and network-level dynamic voltage and frequency scaling (DVFS) in an mSWNoC, the power and thermal profiles can be improved without a significant impact on the overall execution time. We also show that depending on the applications, temperature hotspots can be formed either in the processing cores or in the network infrastructure. The proposed dual-level DVFS is capable of addressing both types of hotspots. In this work we will demonstrate how novel interconnect architectures enabled by the on-chip wireless links coupled with power management strategies can improve the energy and thermal characteristics of a NoC significantly.