Analysis of cache-coherence bottlenecks with hybrid hardware/software techniques

Author:

Marathe Jaydeep1,Mueller Frank1,de Supinski Bronis R.2

Affiliation:

1. North Carolina State University, Raleigh, NC

2. Lawrence Livermore National Laboratory, Livermore, CA

Abstract

Application performance on high-performance shared-memory systems is often limited by sharing patterns resulting in cache-coherence bottlenecks. Current approaches to identify coherence bottlenecks incur considerable run-time overhead and do not scale. We present two novel hardware-assisted coherence-analysis techniques that reduce trace sizes by two orders of magnitude over full traces. First, hardware performance monitoring is combined with capturing stores in software to provide a lossy-trace mechanism, which is an order of magnitude faster than software-instrumentation-based full-tracing and retains accuracy. Second, selected long-latency loads are instrumented via binary rewriting, which provides even higher accuracy and control over tracing, but requires additional overhead.

Publisher

Association for Computing Machinery (ACM)

Subject

Hardware and Architecture,Information Systems,Software

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