What's So Hard About (Mixed-Size) Placement?

Author:

Khasawneh Mohammad1,Madden Patrick H.2

Affiliation:

1. SUNY Binghamton CSD & MathWorks, Binghamton, NY, USA

2. SUNY Binghamton CSD, Binghamton, NY, USA

Publisher

ACM

Reference30 articles.

1. Optimization by Simulated Annealing

2. An Efficient Heuristic Procedure for Partitioning Graphs

3. A. Mirhoseini , A. Goldie , M. Yazgan , J. W. Jiang , E. Songhori , S. Wang , Y.-J. Lee , E. Johnson , O. Pathak , A. Nazi , J. Pak , A. Tong , K. Srinivasa , W. Hang , and E. Tuncer . A graph placement methodology for fast chip design. Nature, 594(June 2021):207--212 , 2021 . A. Mirhoseini, A. Goldie, M. Yazgan, J. W. Jiang, E. Songhori, S. Wang, Y.-J. Lee, E. Johnson, O. Pathak, A. Nazi, J. Pak, A. Tong, K. Srinivasa, W. Hang, and E. Tuncer. A graph placement methodology for fast chip design. Nature, 594(June 2021):207--212, 2021.

4. M. R. Garey and D. S. Johnson . Computers and Intractibility: A Guide to the Theory of NP-Completeness . W.H. Freeman and Co. ,San Francisco, CA, 1979 . page 209 . M. R. Garey and D. S. Johnson. Computers and Intractibility: A Guide to the Theory of NP-Completeness. W.H. Freeman and Co.,San Francisco, CA, 1979. page 209.

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