Physical Design Optimization, From Past to Future

Author:

da Luz Reis Ricardo Augusto1

Affiliation:

1. Universidade Federal do Rio Grande do Sul, Porto Alegre, Brazil

Funder

Capes

CNPq

FAPERGS

Publisher

ACM

Reference11 articles.

1. ANCEAU , François e REIS , Ricardo, Complex Integrated Circuit Design Strategy, IEEE Journal of Solid State Circuits , New York , SC-17 ( 3 ): 459 -- 464 , June 1982 . DOI: 10.1109/JSSC.1982.1051760 10.1109/JSSC.1982.1051760 ANCEAU, François e REIS, Ricardo, Complex Integrated Circuit Design Strategy, IEEE Journal of Solid State Circuits, New York, SC-17(3):459--64, June 1982. DOI: 10.1109/JSSC.1982.1051760

2. REIS ; Ricardo; G OMES , Rogério Figurelli; LUBASZEWSKI , Marcelo. An Efficient Design Methodology for Standard Cell Circuits. In: IEEE INTERNATIONAL SYMPOSIUM on CIRCUITS and SYSTEMS, Espoo, Jun. 7--9, 1988 . Proceedings. New York: IEEE , 1988 . V.2 p. 1213 -- 1216 . DOI: 10.1109/ISCAS.1988.15145 10.1109/ISCAS.1988.15145 REIS; Ricardo; GOMES, Rogério Figurelli; LUBASZEWSKI, Marcelo. An Efficient Design Methodology for Standard Cell Circuits. In: IEEE INTERNATIONAL SYMPOSIUM on CIRCUITS and SYSTEMS, Espoo, Jun. 7--9, 1988. Proceedings. New York: IEEE, 1988. V.2 p. 1213--16. DOI: 10.1109/ISCAS.1988.15145

3. REIS , Ricardo A New Standard Cell CAD Methodology. In: IEEE Custom Integrated Circuits Conference , Portland, Oregon, May 4--7 , 1987 . Proceedings, New York, IEEE, 1987. p. 385--388. REIS, Ricardo A New Standard Cell CAD Methodology. In: IEEE Custom Integrated Circuits Conference, Portland, Oregon, May 4--7, 1987. Proceedings, New York, IEEE, 1987. p. 385--388.

4. A Full Over-the-Cell routing model

5. Transistor Count Reduction by Gate Merging

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