1. A survey of multicore processors
2. DeNovo: Rethinking the Memory Hierarchy for Disciplined Parallelism
3. On Cache Coherency and Memory Consistency Issues in NoC Based Shared Memory Multiprocessor SoC Architectures
4. J. Howard , S. Dighe , Y. Hoskote et al., "A 48-core IA-32 message-passing processor with DVFS in 45nm CMOS," in Solid-State Circuits Conference Digest of Technical Papers (ISSCC) , 2010 IEEE International , 2010 , pp. 108 -- 109 . J. Howard, S. Dighe, Y. Hoskote et al., "A 48-core IA-32 message-passing processor with DVFS in 45nm CMOS," in Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International, 2010, pp. 108--109.
5. Memory models