A High-speed Verilog HDL Simulation Method using a Lightweight Translator

Author:

Kobayashi Ryohei1,Misono Tomohiro2,Kise Kenji2

Affiliation:

1. University of Tsukuba, Japan

2. Tokyo Institute of Technology, Japan

Abstract

Designing with Hardware Description Languages (HDLs) is still the de facto standard way to develop FPGA-based custom computing systems, and RTL simulation is an important step in ensuring that the designed hardware behavior meets the design specification. In this paper, we propose a new high-speed Verilog HDL simulation method. It is based on two previously proposed techniques: ArchHDL and Pyverilog. ArchHDL is used as a simulation engine in the method because the RTL simulation provided by ArchHDL can be parallelized with OpenMP. We use Pyverilog to develop a code translator to convert Verilog HDL source code into ArchHDL code, and due to this, the translator can be realized and its implementation is lightweight. We compare the proposed method with Synopsys VCS, and the experimental results show that the RTL simulation behavior and speed are same as that of Synopsys VCS and up to 5.8x better respectively.

Publisher

Association for Computing Machinery (ACM)

Reference11 articles.

1. Large FPGA Methodology Guide. http://www.xilinx.com/support/documentation/swmanuals/xilinx147/ug872largefpga.pdf. Large FPGA Methodology Guide. http://www.xilinx.com/support/documentation/swmanuals/xilinx147/ug872largefpga.pdf.

2. Shimpei Sato and Kenji Kise . Archhdl: A novel hardware rtl design environment in c++. In Kentaro Sano Dimitrios Soudris Michael Hubner and Pedro C. Diniz editors Applied Reconfigurable Computing volume 9040 of Lecture Notes in Computer Science pages 53 -- 64 . Springer International Publishing 2015 . Shimpei Sato and Kenji Kise. Archhdl: A novel hardware rtl design environment in c++. In Kentaro Sano Dimitrios Soudris Michael Hubner and Pedro C. Diniz editors Applied Reconfigurable Computing volume 9040 of Lecture Notes in Computer Science pages 53--64. Springer International Publishing 2015.

3. Shinya Takamaeda-Yamazaki . Pyverilog: A python-based hardware design processing toolkit for verilog hdl. In Kentaro Sano Dimitrios Soudris Michael Hubner and Pedro C. Diniz editors Applied Reconfigurable Computing volume 9040 of Lecture Notes in Computer Science pages 451 -- 460 . Springer International Publishing 2015 . Shinya Takamaeda-Yamazaki. Pyverilog: A python-based hardware design processing toolkit for verilog hdl. In Kentaro Sano Dimitrios Soudris Michael Hubner and Pedro C. Diniz editors Applied Reconfigurable Computing volume 9040 of Lecture Notes in Computer Science pages 451--460. Springer International Publishing 2015.

4. Synopsys vcs. http://www.synopsys.com/products/simulation/simulation.html. Synopsys vcs. http://www.synopsys.com/products/simulation/simulation.html.

同舟云学术

1.学者识别学者识别

2.学术分析学术分析

3.人才评估人才评估

"同舟云学术"是以全球学者为主线,采集、加工和组织学术论文而形成的新型学术文献查询和分析系统,可以对全球学者进行文献检索和人才价值评估。用户可以通过关注某些学科领域的顶尖人物而持续追踪该领域的学科进展和研究前沿。经过近期的数据扩容,当前同舟云学术共收录了国内外主流学术期刊6万余种,收集的期刊论文及会议论文总量共计约1.5亿篇,并以每天添加12000余篇中外论文的速度递增。我们也可以为用户提供个性化、定制化的学者数据。欢迎来电咨询!咨询电话:010-8811{复制后删除}0370

www.globalauthorid.com

TOP

Copyright © 2019-2024 北京同舟云网络信息技术有限公司
京公网安备11010802033243号  京ICP备18003416号-3