Anaysis of interleaved memory systems using blockage buffers

Author:

Burnett G. J.1,Coffman E. G.2

Affiliation:

1. Index Systems,Inc., Cambridge, MA

2. Pennsylvania State Univ., University Park

Abstract

A model of interleaved memory systems is presented, and the analysis of the model by Monte Carlo simulation is discussed. The simulations investigate the performance of various system structures, i.e. schemes for sending instruction and data requests to the memory system. Performance is measured by determining the distribution of the number of memory modules in operation during a memory cycle. An important observation from these investigations is that separately grouping instruction and data requests for memory can substantially increase the average number of memory modules in operation during a memory cycle. Results of the simulations and an analytical study are displayed for various system structures.

Publisher

Association for Computing Machinery (ACM)

Subject

General Computer Science

Cited by 4 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. High-Performance Memory Systems;The Microarchitecture of Pipelined and Superscalar Computers;1999

2. The impact of distributions and disciplines on multiple processor systems;Communications of the ACM;1979-01

3. A study of interleaved memory systems by trace driven simulation;ACM SIGSIM Simulation Digest;1976-07

4. Interference in multiprocessor computer systems with interleaved memory;Communications of the ACM;1976-06

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