A Series-parallel Mixed Structure FFT Processor

Author:

Jiang Hua1,Xu Wenkai2

Affiliation:

1. School of Electronics and Information and School of Tongke Microelectronics, Nantong University, China

2. School of Electronics and Information, Nantong University, China

Funder

Brand Professional Construction Project of Colleges and Universities in Jiangsu Province

Doctoral Research Initiation Fund Project of Nantong University

Publisher

ACM Press

Reference7 articles.

1. Dai, Y. 2016. Design FFT processor based on FPGA. Int. J. Control Autom. 9, 11, 137--142.

2. Mookherjee, S., DeBrunner, L., and DeBrunner, V. 2015. A low power radix-2 FFT accelerator for FPGA. In 49th Asilomar Conference on Signals, Systems and Computers (Pacific Grove, CA, United states, November 08-11, 2015). IEEE, 447--451.

3. Ma, Y. and Liang, H. 2017. Implementation of a pipeline large-FFT processor based on the FPGA. In 6th International Conference on Communications, Signal Processing, and Systems, CSPS 2017 (Harbin, China, July 14-16, 2017). Springer, 638--644.

4. Wang, X. and Liu, Y. 2006. Full Parallel FFT Based on FPGA. Nanjing Hangkong Hangtian Daxue Xuebao. 38, 1 (Feb. 2006), 96--100.

5. Wang, X. and Liu, Y. 2008. Super-wide band digital I/Q transform algorithm based on FFT and its implementation. Yi Qi Yi Biao Xue Bao. 29, 8 (Aug. 2008), 1714--1718.

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