The Impact of Heterogeneous Logic on Adders and Multipliers in VTR

Author:

Jafarof Navid1ORCID,Kent Kenneth B.1ORCID

Affiliation:

1. Faculty of Computer Science, University of New Brunswick, Fredericton, Canada

Publisher

ACM

Reference14 articles.

1. VPR: a new packing, placement and routing tool for FPGA research

2. Vaughn Betz, Jonathan Rose, and Alexander Marquardt. 2012. Architecture and CAD for deep-submicron FPGAs. Vol. 497. Springer Science & Business Media.

3. Robert Brayton and Alan Mishchenko. 2010. ABC: An academic industrial-strength verification tool. In Computer Aided Verification: 22nd International Conference, CAV 2010, Edinburgh, UK, July 15-19, 2010. Proceedings 22. Springer, 24--40.

4. Odin II - An Open-Source Verilog HDL Synthesis Tool for CAD Research

5. Peter Jamieson and Jonathan Rose. 2005. A verilog RTL synthesis tool for heterogeneous FPGAs. In International Conference on Field Programmable Logic and Applications, 2005. IEEE, 305--310.

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