VST-A: A Foundationally Sound Annotation Verifier

Author:

Zhou Litao1ORCID,Qin Jianxing2ORCID,Wang Qinshi3ORCID,Appel Andrew W.3ORCID,Cao Qinxiang2ORCID

Affiliation:

1. Shanghai Jiao Tong University, Shanghai, China / University of Hong Kong, Hong Kong, China

2. Shanghai Jiao Tong University, Shanghai, China

3. Princeton University, Princeton, USA

Abstract

Program verifiers for imperative languages such as C may be annotation-based, in which assertions and invariants are put into source files and then checked, or tactic-based, where proof scripts separate from programs are interactively developed in a proof assistant such as Coq. Annotation verifiers have been more automated and convenient, but some interactive verifiers have richer assertion languages and formal proofs of soundness. We present VST-A, an annotation verifier that uses the rich assertion language of VST, leverages the formal soundness proof of VST, but allows users to describe functional correctness proofs intuitively by inserting assertions. VST-A analyzes control flow graphs, decomposes every C function into control flow paths between assertions, and reduces program verification problems into corresponding straightline Hoare triples. Compared to existing foundational program verification tools like VST and Iris, in VST-A such decompositions and reductions can nonstructural, which makes VST-A more flexible to use. VST-A's decomposition and reduction is defined in Coq, proved sound in Coq, and computed call-by-value in Coq. The soundness proof for reduction is totally logical, independent of the complicated semantic model (and soundness proof) of VST's Hoare triple. Because of the rich assertion language, not all reduced proof goals can be automatically checked, but the system allows users to prove residual proof goals using the full power of the Coq proof assistant.

Funder

NSF China

DARPA

Publisher

Association for Computing Machinery (ACM)

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1. Verifying Programs with Logic and Extended Proof Rules: Deep Embedding vs. Shallow Embedding;Journal of Automated Reasoning;2024-08-10

2. Verification Condition Generator for Process-Oriented Programs in Reflex Language Using Isabelle/HOL;2024 IEEE 25th International Conference of Young Professionals in Electron Devices and Materials (EDM);2024-06-28

3. Research Report: Not All Move Specifications Are Created Equal : A Case Study on the Formally Verified Diem Payment Network;2024 IEEE Security and Privacy Workshops (SPW);2024-05-23

4. A Formalization of Core Why3 in Coq;Proceedings of the ACM on Programming Languages;2024-01-05

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