Silicon-photonic network architectures for scalable, power-efficient multi-chip systems

Author:

Koka Pranay1,McCracken Michael O.1,Schwetman Herb1,Zheng Xuezhe2,Ho Ron3,Krishnamoorthy Ashok V.2

Affiliation:

1. Sun Labs, Oracle, Austin, TX, USA

2. Sun Labs, Oracle, San Diego, CA, USA

3. Sun Labs, Oracle, Menlo Park, CA, USA

Abstract

Scaling trends of logic, memories, and interconnect networks lead towards dense many-core chips. Unfortunately, process yields and reticle sizes limit the scalability of large single-chip systems. Multi-chip systems break free of these areal limits, but in turn require enormous chip-to-chip bandwidth. The "macrochip" concept presented here integrates multiple many-core processor chips in a single package with silicon-photonic interconnects. This design enables a multi-chip system to approach the performance of a single large die. In this paper we propose three silicon-photonic network designs that provide low-power, high-bandwidth inter-die communication: a static wavelength-routed point-to-point network, a "two-phase" arbitrated network, and a limited-connectivity point-to-point network. We also adapt two existing intra-chip silicon-photonic interconnects: a token-ring-based crossbar and a circuit-switched torus. We simulate a 64-die, 512-core cache-coherent macrochip using all of the above networks with synthetic kernels, and kernels from Splash-2 and PARSEC. We evaluate the networks on performance, optical power and complexity. Despite a narrow data-path width compared to the token-ring or torus, the point-to-point performs 3.3x and 3.9x better respectively. We show that the point-to-point is over 10x more power-efficient than the other networks. We also show that, contrary to electronic network designs, a point-to-point network has the lowest design complexity for an inter-chip silicon-photonic network.

Publisher

Association for Computing Machinery (ACM)

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