Library-Based Placement and Routing in FPGAs with Support of Partial Reconfiguration

Author:

Mao Fubing1,Chen Yi-Chung2,Zhang Wei3,Li Hai (Helen)4,He Bingsheng1

Affiliation:

1. Nanyang Technological University, Nanyang Avenue, Singapore

2. University of Manchester, Manchester, UK

3. Hong Kong University of Science and Technology, Kowloon, Hong Kong

4. University of Pittsburgh, Pennsylvania, USA

Abstract

While traditional Field-Programmable Gate Array design flow usually employs fine-grained tile-based placement, modular placement is increasingly required to speed up the large-scale placement and save the synthesis time. Moreover, the commonly used modules can be pre-synthesized and stored in the library for design reuse to significantly save the design, verification time, and development cost. Previous work mainly focuses on modular floorplanning without module placement information. In this article, we propose a library-based placement and routing flow that best utilizes the pre-placed and routed modules from the library to significantly save the execution time while achieving the minimal area-delay product. The flow supports the static and reconfigurable modules at the same time. The modular information is represented in the B*-Tree structure, and the B*-Tree operations are amended together with Simulated Annealing to enable a fast search of the placement space. Different width-height ratios of the modules are exploited to achieve area-delay product optimization. Partial reconfiguration-aware routing using pin-to-wire abutment is proposed to connect the modules after placement. Our placer can reduce the compilation time by 65% on average with 17% area and 8.2% delay overhead compared with the fine-grained results of Versatile Place and Route through the reuse of module information in the library for the base architecture. For other architectures, the area increase ranges from 8.32% to 25.79%, the delay varies from − 13.66% to 19.79%, and the runtime improves by 43.31% to 77.2%.

Funder

Hong Kong SAR

MoE AcRF Tier 2

Publisher

Association for Computing Machinery (ACM)

Subject

Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Computer Science Applications

Reference52 articles.

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2. Hierarchical FPGA placement

3. Wires on demand: Run-time communication synthesis for reconfigurable computing;Athanas P.;FPL,2007

4. Pritha Banerjee etal 2011. Floorplanning for partially reconfigurable FPGAs. TCAD 30 1 (2011). 10.1109/TCAD.2010.2079390 Pritha Banerjee et al. 2011. Floorplanning for partially reconfigurable FPGAs. TCAD 30 1 (2011). 10.1109/TCAD.2010.2079390

5. Fast Unified Floorplan Topology Generation and Sizing on Heterogeneous FPGAs

Cited by 1 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. HLS Enabled Partially Reconfigurable Module Implementation;Lecture Notes in Computer Science;2018

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