Crossing the machine interface

Abstract

The concepts and theory behind a specific type of hardware accelerator, oar “assist”, are presented. Such accelerators are specific extensions to an existing, generalized data processor architecture. Both the software system and the hardware implementation are changed by the extensions. For the accelerators discussed here, the hardware implementation is accomplished solely in microcode. The generalized architecture can be compatible across a line of data processors. The accelerators are defacto extensions to the basic architecture and are normally only defined on a subset of the processor line. These architectural extensions consist of functions migrated from “above” the generalized architecture (i.e. software functions) into the processor architecture and processor implementation. The accelerators provide a method of improving system performance that is complementary to improving performance through modification of the generalized processor architecture itself or the underlying circuitry implementation.