Machine Learning for Testing Machine-Learning Hardware

Author:

Chaudhuri Arjun1,Talukdar Jonti1,Chakrabarty Krishnendu1

Affiliation:

1. Duke University

Funder

Semiconductor Research Corporation

Publisher

ACM

Reference16 articles.

1. B. Reagen , " Ares: A framework for quantifying the resilience of deep neural networks," in DAC , 2018 . B. Reagen et al., "Ares: A framework for quantifying the resilience of deep neural networks," in DAC, 2018.

2. G. Li , " Understanding error propagation in deep learning neural network (DNN) accelerators and applications," in ACM SC , 2017 . G. Li et al., "Understanding error propagation in deep learning neural network (DNN) accelerators and applications," in ACM SC, 2017.

3. J. J. Zhang , " Analyzing and mitigating the impact of permanent faults on a systolic array based neural network accelerator," in VLSI Test Symposium , 2018 . J. J. Zhang et al., "Analyzing and mitigating the impact of permanent faults on a systolic array based neural network accelerator," in VLSI Test Symposium, 2018.

4. S. Kundu , " Toward functional safety of systolic array-based deep learning hardware accelerators," TVLSI , 2021 . S. Kundu et al., "Toward functional safety of systolic array-based deep learning hardware accelerators," TVLSI, 2021.

5. A. Chaudhuri , " C-testing of AI accelerators," in ATS , 2020 . A. Chaudhuri et al., "C-testing of AI accelerators," in ATS, 2020.

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