Evaluating the Security of eFPGA-Based Redaction Algorithms

Author:

Rezaei Amin1,Afsharmazayejani Raheel2,Maynard Jordan1

Affiliation:

1. California State University Long Beach

2. University of Calgary, Calgary, Alberta, Canada

Publisher

ACM

Reference57 articles.

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2. Functional obfuscation of hardware accelerators through selective partial design extraction onto an embedded FPGA;Hu B.;Great Lakes Symposium on VLSI (GLSVLSI)),2019

3. P. Mohan , O. Atli , J. Sweeney , O. Kibar , L. Pileggi , and K. Mai , " Hardware redaction via designer-directed fine-grained eFPGA insertion," In Design , Automation & Test in Europe Conference & Exhibition (DATE) , pp. 1186 -- 1191 , 2021 . P. Mohan, O. Atli, J. Sweeney, O. Kibar, L. Pileggi, and K. Mai, "Hardware redaction via designer-directed fine-grained eFPGA insertion," In Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 1186--1191, 2021.

4. Exploring eFPGA-based redaction for IP protection;Bhandari J.;IEEE/ACM International Conference On Computer Aided Design (ICCAD),2021

5. J. Bhandari , A. K. Thalakkattu Moosa , B. Tan , C. Pilato , G. Gore , X. Tang , S. Temple , P. -E. Gaillardon , and R. Karri , " Not all fabrics are created equal: Exploring eFPGA parameters for IP redaction," In arXiv.2111.04222 [cs.CR] , 2021 . J. Bhandari, A. K. Thalakkattu Moosa, B. Tan, C. Pilato, G. Gore, X. Tang, S. Temple, P. -E. Gaillardon, and R. Karri, "Not all fabrics are created equal: Exploring eFPGA parameters for IP redaction," In arXiv.2111.04222 [cs.CR], 2021.

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