1. Y. Ma , H. Ren , B. Khailany , H. Sikka , L. Luo , K. Natarajan , and B. Yu , " High performance graph convolutional networks with applications in testability analysis," in Proc . DAC , 2019 , pp. 1 -- 6 . Y. Ma, H. Ren, B. Khailany, H. Sikka, L. Luo, K. Natarajan, and B. Yu, "High performance graph convolutional networks with applications in testability analysis," in Proc. DAC, 2019, pp. 1--6.
2. H. Geng , Y. Ma , Q. Xu , J. Miao , S. Roy , and B. Yu , " High-speed adder design space exploration via graph neural processes," IEEE TCAD , 2021 . H. Geng, Y. Ma, Q. Xu, J. Miao, S. Roy, and B. Yu, "High-speed adder design space exploration via graph neural processes," IEEE TCAD, 2021.
3. Machine Learning for Electronic Design Automation: A Survey
4. Wordrev: Finding word-level structures in a sea of bit-level gates;Li W.;Proc. HOST. IEEE,2013
5. Deep learning-based circuit recognition using sparse mapping and level-dependent decaying sum circuit representations;Fayyazi A.;Proc. DATE,2019