Scaled-CBSC

Author:

Yu Shuyuan1,Tan Sheldon X.-D.1

Affiliation:

1. University of California

Funder

NSF (National Science Foundation)

Publisher

ACM

Reference20 articles.

1. S. Venkataramani , S. T. Chakradhar , K. Roy , and A. Raghunathan , " Approximate computing and the quest for computing efficiency," in 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC) , pp. 1 -- 6 , IEEE , 2015 . S. Venkataramani, S. T. Chakradhar, K. Roy, and A. Raghunathan, "Approximate computing and the quest for computing efficiency," in 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC), pp. 1--6, IEEE, 2015.

2. P. Kulkarni , P. Gupta , and M. Ercegovac , " Trading accuracy for power with an underdesigned multiplier architecture," in 2011 24th Internatioal Conference on VLSI Design , pp. 346 -- 351 , IEEE , 2011 . P. Kulkarni, P. Gupta, and M. Ercegovac, "Trading accuracy for power with an underdesigned multiplier architecture," in 2011 24th Internatioal Conference on VLSI Design, pp. 346--351, IEEE, 2011.

3. K. Bhardwaj , P. S. Mane , and J. Henkel , " Power-and area-efficient approximate wallace tree multiplier for error-resilient systems," in Fifteenth International Symposium on Quality Electronic Design , pp. 263 -- 269 , IEEE , 2014 . K. Bhardwaj, P. S. Mane, and J. Henkel, "Power-and area-efficient approximate wallace tree multiplier for error-resilient systems," in Fifteenth International Symposium on Quality Electronic Design, pp. 263--269, IEEE, 2014.

4. B. S. Prabakaran , S. Rehman , M. A. Hanif , S. Ullah , G. Mazaheri , A. Kumar , and M. Shafique , " Demas: An efficient design methodology for building approximate adders for fpga-based systems," in 2018 Design , Automation & Test in Europe Conference & Exhibition (DATE) , pp. 917 -- 920 , IEEE, 2018 . B. S. Prabakaran, S. Rehman, M. A. Hanif, S. Ullah, G. Mazaheri, A. Kumar, and M. Shafique, "Demas: An efficient design methodology for building approximate adders for fpga-based systems," in 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 917--920, IEEE, 2018.

5. S. Ullah , S. Rehman , B. S. Prabakaran , F. Kriebel , M. A. Hanif , M. Shafique , and A. Kumar , " Area-optimized low-latency approximate multipliers for fpga-based hardware accelerators," in Proceedings of the 55th Annual Design Automation Conference , pp. 1 -- 6 , 2018 . S. Ullah, S. Rehman, B. S. Prabakaran, F. Kriebel, M. A. Hanif, M. Shafique, and A. Kumar, "Area-optimized low-latency approximate multipliers for fpga-based hardware accelerators," in Proceedings of the 55th Annual Design Automation Conference, pp. 1--6, 2018.

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1. Fast and Scaled Counting-Based Stochastic Computing Divider Design;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2024-08

2. Accurate yet Efficient Stochastic Computing Neural Acceleration with High Precision Residual Fusion;2023 Design, Automation & Test in Europe Conference & Exhibition (DATE);2023-04

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