CP-SRAM

Author:

Zhang He1,Jiang Linjun1,Wu Jianxin1,Chen Tingran1,Liu Junzhan1,Kang Wang1,Zhao Weisheng1

Affiliation:

1. Beihang University, Beijing, China

Publisher

ACM

Reference33 articles.

1. A Charge-Domain Scalable-Weight In-Memory Computing Macro With Dual-SRAM Architecture for Precision-Scalable DNN Accelerators

2. A. Krizhevsky , I. Sutskever , and G. E. Hinton , " ImageNet classification with deep convolutional neural networks," in Proc . Adv. Neural Inf. Process. Syst. , pp. 1097 -- 1105 , 2012 A. Krizhevsky, I. Sutskever, and G. E. Hinton, "ImageNet classification with deep convolutional neural networks," in Proc. Adv. Neural Inf. Process. Syst., pp. 1097--1105, 2012

3. X. Yang , B. Yan , H. Li , and Y. Chen , " ReTransformer: ReRAM-based processing-in-memory architecture for transformer acceleration," IEEE/ACM ICCAD, San Diego , USA , pp. 1 -- 9 , 2020 . X. Yang, B. Yan, H. Li, and Y. Chen, "ReTransformer: ReRAM-based processing-in-memory architecture for transformer acceleration," IEEE/ACM ICCAD, San Diego, USA, pp. 1--9, 2020.

4. C3SRAM: An In-Memory-Computing SRAM Macro Based on Robust Capacitive Coupling Computing Mechanism

5. Two-Direction In-Memory Computing Based on 10T SRAM With Horizontal and Vertical Decoupled Read Ports

Cited by 5 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. PipeCIM: A High-Throughput Computing-In-Memory Microprocessor With Nested Pipeline and RISC-V Extended Instructions;IEEE Transactions on Circuits and Systems I: Regular Papers;2024-07

2. An End-to-End In-Memory Computing System Based on a 40-nm eFlash-Based IMC SoC: Circuits, Toolchains, and Systems Co-Design Framework;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2024-06

3. RDCIM: RISC-V Supported Full-Digital Computing-in-Memory Processor With High Energy Efficiency and Low Area Overhead;IEEE Transactions on Circuits and Systems I: Regular Papers;2024-04

4. Probabilistic Compute-in-Memory Design for Efficient Markov Chain Monte Carlo Sampling;IEEE Transactions on Circuits and Systems I: Regular Papers;2024-02

5. A Hierarchically Reconfigurable SRAM-Based Compute-in-Memory Macro for Edge Computing;2023 IEEE 5th International Conference on Artificial Intelligence Circuits and Systems (AICAS);2023-06-11

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