BlueScale

Author:

Jiang Zhe1,Yang Kecheng2,Audsley Neil3,Fisher Nathan4,Shi Weisong4,Dong Zheng4

Affiliation:

1. ARM Ltd, UK

2. Texas State University

3. University of London, UK

4. Wayne State University

Publisher

ACM

Reference21 articles.

1. SEBASTIAN Anthony . 2017. IBM first 5nm chip. Ars Technica ( 2017 ). SEBASTIAN Anthony. 2017. IBM first 5nm chip. Ars Technica (2017).

2. ARM. 1995. AMBA AXI 5.0. https://developer.arm.com/architectures. ARM. 1995. AMBA AXI 5.0. https://developer.arm.com/architectures.

3. Neil Audsley . 2013 . Memory architecture for NoC-based real-time mixed criticality systems . Proc. WMC, RTSS (2013), 37--42. Neil Audsley. 2013. Memory architecture for NoC-based real-time mixed criticality systems. Proc. WMC, RTSS (2013), 37--42.

4. EEMBC. [n.d.]. EEMBC benchmark. https://www.eembc.org/autobench/. EEMBC. [n.d.]. EEMBC benchmark. https://www.eembc.org/autobench/.

5. Renesas Electronics. [n.d.]. Renesas: Automotive Use Cases. https://www.renesas.com/solutions/automotive.html. Renesas Electronics. [n.d.]. Renesas: Automotive Use Cases. https://www.renesas.com/solutions/automotive.html.

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