Dataflow-Architecture Co-Design for 2.5D DNN Accelerators using Wireless Network-on-Package
Author:
Affiliation:
1. Universitat Politècnica de Catalunya, Barcelona, Spain
2. Georgia Institute of Technology, Atlanta, GA, USA
Publisher
ACM
Link
https://dl.acm.org/doi/pdf/10.1145/3394885.3431537
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3. M. M. Ahmed N. Mansoor and A. Ganguly. 2018. An Asymmetric Energy Efficient One-to-Many Traffic-Aware Wireless Network-in-Package Interconnection Architecture for Multichip Systems. In IGSC. M. M. Ahmed N. Mansoor and A. Ganguly. 2018. An Asymmetric Energy Efficient One-to-Many Traffic-Aware Wireless Network-in-Package Interconnection Architecture for Multichip Systems. In IGSC.
4. G. Ascia V. Catania A. Mineo etal 2020. Improving Inference Latency and Energy of DNNs through Wireless Enabled Multi-Chip-Module-based Architectures and Model Parameters Compression. In NOCS. G. Ascia V. Catania A. Mineo et al. 2020. Improving Inference Latency and Energy of DNNs through Wireless Enabled Multi-Chip-Module-based Architectures and Model Parameters Compression. In NOCS.
5. The last barrier: on-chip antennas
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