1. Enhancing ASIC Technology Mapping via Parallel Supergate Computing;2024 2nd International Symposium of Electronics Design Automation (ISEDA);2024-05-10
2. Scheduling and Physical Design;Proceedings of the 2024 International Symposium on Physical Design;2024-03-12
3. In Medio Stat Virtus*: Combining Boolean and Pattern Matching;2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC);2024-01-22
4. Physical Implementation;FPGA EDA;2024
5. AiMap: Learning to Improve Technology Mapping for ASICs via Delay Prediction;2023 IEEE 41st International Conference on Computer Design (ICCD);2023-11-06