Short Reasons for Long Vectors in HPC CPUs: A Study Based on RISC-V-Reference-Cited by-同舟云学术

Short Reasons for Long Vectors in HPC CPUs: A Study Based on RISC-V

Published:2023-11-12 Issue: Volume: Page:
ISSN:
Container-title:Proceedings of the SC '23 Workshops of The International Conference on High Performance Computing, Network, Storage, and Analysis
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Author:

Vizcaino Pablo¹^ORCID,Ieronymakis Georgios²^ORCID,Dimou Nikolaos²^ORCID,Papaefstathiou Vassilis²^ORCID,Labarta Jesus¹^ORCID,Mantovani Filippo¹^ORCID

Affiliation:

1. Barcelona Supercomputing Center, Spain

2. Foundation for Research and Technology - Hellas (FORTH), Greece, Greece

Funder

European High Performance Computing Joint Undertaking

MCIN/AEI

Publisher

ACM

Link

https://dl.acm.org/doi/pdf/10.1145/3624062.3624231

Reference16 articles.

1. Constantino Gómez Crespo Marc Casas Guix Filippo Mantovani and Erich Focht. 2020. Optimizing sparse matrix-vector multiplication in NEC SX-Aurora vector engine. (2020). https://upcommons.upc.edu/handle/2117/192586 Constantino Gómez Crespo Marc Casas Guix Filippo Mantovani and Erich Focht. 2020. Optimizing sparse matrix-vector multiplication in NEC SX-Aurora vector engine. (2020). https://upcommons.upc.edu/handle/2117/192586

2. Architectural Considerations for Exascale Supercomputing

3. Mate Kovač 2023. FAUST: design and implementation of a pipelined RISC-V vector floating-point unit. Microprocessors and Microsystems ( 2023 ), 104762. Mate Kovač 2023. FAUST: design and implementation of a pipelined RISC-V vector floating-point unit. Microprocessors and Microsystems (2023), 104762.

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