Affiliation:
1. University of Texas at Dallas, TX, USA
Abstract
This works presents a Design Space Exploration (DSE) method for Behavioral IPs (BIPs) given in ANSI-C or SystemC to find the smallest micro-architecture for a specific target latency. Previous work on High-Level Synthesis (HLS) DSE mainly focused on finding a tradeoff curve with Pareto-optimal designs. HLS is, however, a single process (component) synthesis method. Very often, the latency of the components requires a specific fixed latency when inserted within a larger system. This work presents a fast multi-threaded method to find the smallest micro-architecture for a given BIP and target latency by discriminating between all different exploration
knobs
and exploring these concurrently. Experimental results show that our proposed method is very effective and comprehensive results compare the quality of results vs. the speedup of your proposed explorer.
Publisher
Association for Computing Machinery (ACM)
Subject
Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Computer Science Applications
Reference32 articles.
1. Efficient design space exploration for application specific systems-on-a-chip
2. Cadence Status. 2016. Homepage. Retrieved from www.cadence.com. Cadence Status. 2016. Homepage. Retrieved from www.cadence.com.
3. Benjamin Carrion Schafer. 2014. Allocation of FPGA DSP-macros in multi-process high-level synthesis systems. In ASP-DAC. 616--621. Benjamin Carrion Schafer. 2014. Allocation of FPGA DSP-macros in multi-process high-level synthesis systems. In ASP-DAC. 616--621.
4. Probabilistic multi-knob high-level synthesis design space exploration acceleration;Schafer B. Carrion;IEEE Trans. Comput.-Aid. Des. Integr. Circ. Syst.,2015
5. S2CBench: Synthesizable SystemC Benchmark Suite for High-Level Synthesis
Cited by
19 articles.
订阅此论文施引文献
订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献