Synthesis of saturation arithmetic architectures-Reference-Cited by-同舟云学术

Synthesis of saturation arithmetic architectures

Published:2003-07 Issue:3 Volume:8 Page:334-354
ISSN:1084-4309
Container-title:ACM Transactions on Design Automation of Electronic Systems
language:en
Short-container-title:ACM Trans. Des. Autom. Electron. Syst.

Author:

Constantinides G. A.¹,Cheung P. Y. K.¹,Luk W.¹

Affiliation:

1. Imperial College of Science, Technology and Medicine, London, United Kingtom

Abstract

This paper describes a synthesis technique for automating the design of linear Digital Signal Processing (DSP) systems such as digital filters. The proposed methodology makes optimized use of saturation arithmetic to produce a small design implemented directly in hardware. An analytical technique is proposed to estimate the saturation error resulting from a particular implementation, and an optimization procedure is introduced to aim for the smallest implementation satisfying user-specified bounds on saturation and roundoff error. Results are presented illustrating significant speedup and area reduction compared with standard DSP design techniques: up to 22% improvement in area and 28% improvement in speed have been obtained on Field Programmable Gate Array (FPGA) implementations.

Publisher

Association for Computing Machinery (ACM)

Subject

Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Computer Science Applications

Link

https://dl.acm.org/doi/pdf/10.1145/785411.785415

Reference19 articles.

1. Altera Corporation. 1998. Altera Databook. San Jose: Altera Corporation. Altera Corporation. 1998. Altera Databook. San Jose: Altera Corporation.

2. Chung K.-L. 1974. A Course in Probability Theory. Academic Press New York. Chung K.-L. 1974. A Course in Probability Theory. Academic Press New York.

3. Constantinides G. A. 2001. High Level Synthesis and Word Length Optimization of Digital Signal Processing Systems. Ph.D. thesis University of London. Constantinides G. A. 2001. High Level Synthesis and Word Length Optimization of Digital Signal Processing Systems. Ph.D. thesis University of London.

Cited by 16 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Exploiting a Blink of Measurement Saturation Towards Hardware-Efficient Compressed Sensing Encoder Design;2022 IEEE International Symposium on Circuits and Systems (ISCAS);2022-05-28

2. An Image-Driven Uncertainty Inverse Method for Sheet Metal Forming Problems;Journal of Mechanical Design;2021-12-06

3. A parallel beamforming system with real-time implementation;Multimedia Tools and Applications;2019-05-07

4. An Efficient Hardware-Based Higher Radix Floating Point MAC Design;ACM Transactions on Design Automation of Electronic Systems;2014-11-18

5. FPGA multi-filter system for speech enhancement via multi-criteria optimization;Applied Soft Computing;2014-08