1. Attention based on Software and Hardware Co-design[C]//2022 IEEE 9th International Conference on Cyber Security and Cloud Computing (CSCloud)/2022 IEEE 8th International Conference on Edge Computing and Scalable Cloud (EdgeCom);Xu D;IEEE
2. Hardware-friendly compression and hardware acceleration for transformer: A survey
3. Lu L Jin Y Bi H Sanger: A co-design framework for enabling sparse attention using reconfigurable architecture[C]//MICRO-54: 54th Annual IEEE/ACM International Symposium on Microarchitecture. 2021: 977-991.
4. Full-Digital Bitline-Transpose CIM-based Sparse Transformer Accelerator With Pipeline/Parallel Reconfigurable Modes[J];Tu F;IEEE Journal of Solid-State Circuits,2022
5. Rizk R, Rizk D, Rizk F, A Resource-Saving Energy-Efficient Reconfigurable Hardware Accelerator for BERT-based Deep Neural Network Language Models using FFT Multiplication[C]//2022 IEEE International Symposium on Circuits and Systems (ISCAS). IEEE, 2022: 1675-1679.