Debugging and verifying SoC designs through effective cross-layer hardware-software co-simulation-Reference-Cited by-同舟云学术

Debugging and verifying SoC designs through effective cross-layer hardware-software co-simulation

Published:2016-06-05 Issue: Volume: Page:
ISSN:
Container-title:Proceedings of the 53rd Annual Design Automation Conference
language:
Short-container-title:

Author:

Campbell Keith¹,He Leon¹,Yang Liwei²,Gurumani Swathi³,Rupnow Kyle³,Chen Deming¹

Affiliation:

1. University of Illinois at Urbana-Champaign

2. Nanyang Technological University

3. Advanced Digital Sciences Center, Singapore

Funder

Semiconductor Research Corporation

Agency for Science, Technology and Research

Publisher

ACM

Link

https://dl.acm.org/doi/pdf/10.1145/2897937.2898002

Reference20 articles.

1. High-Level Synthesis for FPGAs: From Prototyping to Deployment

2. Xilinx Inc. Vivado High-Level Synthesis. http://www.xilinx.com/products/design-tools/vivado/integration/esl-design/hls/index.htm. Xilinx Inc. Vivado High-Level Synthesis . http://www.xilinx.com/products/design-tools/vivado/integration/esl-design/hls/index.htm.

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