DAG-aware logic synthesis of datapaths

Author:

Yu Cunxi1,Ciesielski Maciej1,Choudhury Mihir2,Sullivan Andrew2

Affiliation:

1. University of Massachusetts, Amherst, MA

2. IBM T.J Watson Research Center, Yorktown Heights, NY

Funder

National Science Foundation

Publisher

ACM

Cited by 6 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Directed Acyclic Graph-Based Datapath Synthesis Using Graph Isomorphism and Gate Reconfiguration;Chips;2024-06-04

2. Logic Synthesis;FPGA EDA;2024

3. Invited Paper: Verilog-to-PyG - A Framework for Graph Learning and Augmentation on RTL Designs;2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD);2023-10-28

4. Equality Saturation for Datapath Synthesis: A Pathway to Pareto Optimality;2023 60th ACM/IEEE Design Automation Conference (DAC);2023-07-09

5. Early-stage automated accelerator identification tool for embedded systems with limited area;Proceedings of the 39th International Conference on Computer-Aided Design;2020-11-02

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