Author:
Papadogiannakis Antonis,Loutsis Laertis,Papaefstathiou Vassilis,Ioannidis Sotiris
Cited by
14 articles.
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1. FPGA Based Memory Security and Error Correction System for RISC-V Processor;2023 3rd International Conference on Frontiers of Electronics, Information and Computation Technologies (ICFEICT);2023-05
2. Hardware Based RISC-V Instruction Set Randomization;2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA);2022-10-28
3. Morpheus II: A RISC-V Security Extension for Protecting Vulnerable Software and Hardware;2021 IEEE International Symposium on Hardware Oriented Security and Trust (HOST);2021-12-12
4. On Architectural Support for Instruction Set Randomization;ACM Transactions on Architecture and Code Optimization;2020-12-22
5. Moving Target Defense Considerations in Real-Time Safety- and Mission-Critical Systems;Proceedings of the 7th ACM Workshop on Moving Target Defense;2020-11-09